Samsung introduces its first 3nm chip which will power devices to be unveiled next week

Samsung has just introduced the new Exynos W1000, an SoC made for wearable devices such as the upcoming Galaxy Watch 7 and the premium Galaxy Watch Ultra. Both timepieces are expected to be unveiled a week from today, on July 10th, during the next Galaxy Unpacked event. The two smartwatches will be joined by the Galaxy Z Flip 6, the Galaxy Z Fold 6, the Galaxy Buds 3, and the new Galaxy Ring.

The Exynos W1000 chip is built by Samsung Foundry using its 3nm process node. It features a five-core CPU which includes one Cortex-A78 CPU core and four Cortex-A55 CPU cores. Samsung claims that the SoC will launch apps 2.7 times faster and  "smoothly switch between multiple apps." The Exynos W1000 chip will also deliver 3.4x faster single-core performance and 3.7x faster multi-core performance. That is in comparison with the Exynos W930 chipset that powers the Galaxy Watch 6.

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Back in May, we told you that the first Samsung device to use a 3nm chip could be the Galaxy Watch 7 and that appears to be the case since the 3nm Snapdragon 8 Gen 4 won't be found inside a Samsung device until next year. One potential drawback is that the GPU used with the Exynos W1000, the ARM Mali-G68 MP2, is the same as the one used with the Exynos W930 chip and supports displays with resolutions up to 960 x 540 pixels. 

The Exynos W1000 SoC does support a 2.5D always-on display (AOD) for smartwatches. That's because the chip features a dedicated low-power display processor that allows the display to be on at all times allowing users to have the time ready to view 24/7 along with notifications, calls, and more.

Thanks to the 3nm process node, the Exynos W1000 should help the Galaxy Watch 7 and Galaxy Watch Ultra deliver improved battery life. Samsung says, "Through its efficient low power design based on a 3nm process and upgrade to LPDDR5 memory, the Exynos W1000 allows you to enjoy premium performance while using your smartwatch for longer."

Samsung Foundry's 3nm process node includes the use of Gate-All-Around (GAA) transistors that allow the gate to come into contact with the channel on all four sides which reduces current leaks, increases the drive current, and improves the performance of the transistor thanks to improved electrical signals that go through and between the transistors. This is achieved by using vertically placed horizontal nanosheets. TSMC won't use GAA until it starts production of 2nm chips next year.