Apple expected to make unusual decision about the A20 chips powering 2026's iPhone 18 line

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Crowds form at the Apple Store as another new iPhone model is released.
Always looking to top the competition, Apple held its nose and paid the higher silicon wafer prices that TSMC charged for 3nm production starting in 2023. Since it orders in huge volumes, Apple got to reserve most of of TSMC's initial 3nm production capacity. As a result, from September 2023 and running for more than a year afterward, the iPhone 15 Pro and iPhone 15 Pro Max were the only smartphones powered by an SoC built using a 3nm node.

Later this year TSMC will start mass-producing chips using its 2nm node. Even though things are going well for TSMC with trial production of 2nm silicon showing a 60% yield, Apple is planning on using TSMC's third-generation 3nm node to produce the A19 and A19 Pro application processors for this year's iPhone 17. Even more surprising, there is talk about Apple sticking with the same node for the A20 chip line that will power the 2026 iPhone 18 models instead of moving ahead to 2nm.

Apple might have made a decision not to pay up for the silicon wafers that are the foundation that chips are built on. When the 3nm process node was introduced by TSMC, the foundry raised its prices to $20,000 for each wafer. That was a 25% hike from the $16,000 that the foundry charged for each wafer used for 5nm production. Each 300mm wafer could yield approximately 785 A18 chipsets assuming a hypothetical 100% yield. It's more likely that TSMC generates a yield in the range of 65% to 70% which would result in 510 to 550 A18 chips manufactured on one $20,000 wafer. Keep in mind that this is just an off-the-back of the envelope estimate.


Not wanting to deal with another hike in wafer prices for 2nm, Apple might hold off on moving to the new node until the A21 and A21 Pro APs are built for the 2027 iPhone19 series. But that doesn't mean that Apple won't be improving its silicon before then. GF Securities' Jeff Pu says that starting with the A20 and A20 Pro on the 2026 iPhone 18 line, TSMC will use Chip-on-Wafer-on-Substrate (CoWoS) packaging.

This packaging allows for tighter integration of various parts of a chip including the Neural Engine, GPU cluster, cache, performance and efficiency cores, and other components. This kind of packaging not only saves space but also delivers improved efficiency. By reducing the path lengths and increasing data transfer rates, performance can be improved.

Sure, watching process node numbers shrink leading to improved chip performance and efficiency is kind of cool. But there are other aspects to semiconductor manufacturing that can also lead to improvements without relying on Moore's Law.
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